Research ArticleNANOMATERIALS

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

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Science Advances  01 Jan 2016:
Vol. 2, no. 1, e1501101
DOI: 10.1126/sciadv.1501101
  • Fig. 1 Characterization of nanoscale charge confinement in AuNP FGs and their large-scale assembly for the wearable CTFM array.

    (A) Schematic showing the process of charge injection to an AuNP FG using a conductive AFM tip. The inset shows the magnified cross-sectional structure of an FG cell (red dashed box) and the charge injection mechanism. (B) Representative topographic AFM image coupled with EFM data (top) showing the nanoscale charge confinement capability of AuNPs. Magnified image of the character “N,” showing particle-level charge confinement within sub–100-nm width (left bottom, red dashed box) and the corresponding EFM image (middle bottom). Comparison of charge retention characteristics between AuNPs and an Au film (right bottom). (C) Photograph of a 22 × 22 wearable multiplexed CTFM array (top). The magnified image shows four memory pixels interconnected with word lines and bit lines (bottom). (D) Schematic showing the LB assembly process (top) and a magnified view (bottom) of the channel area of a single CTFM (red dashed box) with AuNP FG assembled using the LB method. (E) Representative integrated system composed of a CTFM array, voltage amplifiers, and ECG electrodes (top); its applied form on human skin (bottom left); and its magnified view in stretched mode (bottom right, black dashed box).

  • Fig. 2 Large-area and high-density assembly of AuNPs.

    (A) TEM images of AuNPs assembled using the LB method. The insets show magnified TEM images. (B) Images before (left) and after (right) LB assembly of AuNPs on Tox. The insets show the corresponding schematics for the cross-sectional structure of the FG cell. (C) AFM images and quantitative spatial analysis of AuNPs assembled using the LB method at nine locations [right, red dashed boxes in (B)]. (D) TEM images of the CTFM (left). The inset shows a TEM image of the three-layer stacked CTFM. Magnified TEM image showing a detailed cross-sectional structure of the CTFM and uniform AuNP FG embedded in dielectrics (right, red box). (E) High-resolution TEM image showing a detailed structure of the dielectric-AuNP interface [blue box in (D)]. (F) Scanning TEM (STEM) image showing a cross-sectional structure of the CTFM (top left), quantitative EDS analysis results obtained at the spots marked in the STEM image with colored asterisks (top right), and EDS analysis results obtained along the yellow arrow shown in the STEM image (bottom).

  • Fig. 3 Electrical and mechanical characterizations of an AuNP CTFM.

    (A) Capacitance-voltage (C-V) hysteresis curves of FG cells containing different FGs, obtained from 30 FG cells of each FG. The amplitude of the applied AC signal is 30 mV, and its frequency is 1 MHz. The inset shows a schematic of the experimental setup. (B) Cumulative probability data of accumulation capacitances of the FG cells containing different FGs. (C) Schematic of experimental setup for two-dimensional injection of different amounts of charges into the AuNP FG assembled using the LB method. The numbers indicate the sequential order of charge injection performed with different bias conditions. (D) EFM image of the FG cell containing different amounts of charges at different locations by two-dimensional injection of charges. (E) Transfer characteristics of a CTFM pixel after PGM/ERS operation with different voltages, showing four states. (F) PGM/ERS speed characteristics of the CTFM pixel with different operation voltages. (G) Retention characteristics of the CTFM pixel for each possible state. (H) Endurance characteristics of the CTFM pixel. (I) Schematic of the CTFM array in NOR configuration. Dashed boxes indicate the selected memory pixel (red) and manipulated peripheral pixels (blue) for a disturbance test verifying the degree of influence on the electrical state of the selected pixel, induced by manipulation of the peripheral pixels. (J) Transfer curves measured from the erased memory pixel of the initial condition and the inhibited condition in which the PGM bias on WL1 for manipulating the Pa pixel and different inhibition biases on BL3 are applied simultaneously. (K) Transfer curves measured from the programmed memory pixel of the initial condition and the inhibited condition in which the ERS bias on BL3 for manipulating the Pb pixel and different inhibition biases on WL1 are applied simultaneously. (L) Cumulative probability data of the multilevel states obtained from 20 memory pixels. (M and N) FEA results showing the distribution of the maximum principal strain on the entire structure and active region (inset) of the CTFM array [strain of (M), 0%; strain of (N), 20%]. (O and P) Transfer curves of the CTFM pixel after conducting PGM/ERS operation under (O) various applied strains and (P) various stretched cycles of 20% strain.

  • Fig. 4 System-level demonstration of storing heart rates in the AuNP CTFM array.

    (A) Microscopic image of the pseudo-CMOS inverter (top) and schematic circuit diagram (bottom). (B) Voltage transfer characteristics of the pseudo-CMOS inverter (dashed line, simulation results; solid line, experimental results) with various biasing voltages (VSS when VDD is fixed to 6.3 V). (C) Signal gain of the inverter measured with respect to the input voltage (VIN) under various biasing conditions (VSS when VDD is fixed to 6.3 V). The inset shows the maximum gain with respect to VSS. (D) Sinusoidal input signal (black, 40 mVp-p, 10 Hz) and output signal (red) amplified by the pseudo-CMOS inverter. (E) ECG signal containing a single R peak acquired using fabricated stretchable electrodes (left) and commercial electrodes (right). (F) Measured temporal change of the resting heart rate before exercise and after exercise. (G and H) Heart rate recovery data and corresponding elapsed time data retrieved from the CTFM array: (G) immediately after data storage and (H) 6 hours after data storage.

Supplementary Materials

  • Supplementary material for this article is available at http://advances.sciencemag.org/cgi/content/full/2/1/e1501101/DC1

    Text

    Fig. S1. Original data corresponding to Fig. 1B.

    Fig. S2. Fabrication process of the CTFM array.

    Fig. S3. Fabrication process of the pseudo-CMOS inverter array.

    Fig. S4. TEM images of AuNP FG assembled using the LB method after the Box deposition using the PEALD process.

    Fig. S5. TEM-EDS analysis of AuNPs embedded in an FG cell.

    Fig. S6. Energy band diagrams of CTFM under three representative bias conditions.

    Fig. S7. EFM images of the FG cell containing different amounts of charges at different locations according to the elapsed time after charge injection.

    Fig. S8. PGM/ERS characteristics with operation voltages.

    Fig. S9. PGM/ERS speed analysis of the CTFM array.

    Fig. S10. Retention characteristics of a CTFM pixel for different memory states.

    Fig. S11. Retention characteristics of the programmed state (30 V, 0.1 s) and the erased state (−40 V, 0.1 s).

    Fig. S12. Changes in the transfer curves of a CTFM pixel after repetitive PGM and ERS cycles.

    Fig. S13. Changes in transfer curves of a CTFM pixel (selected one) after programming or erasing peripheral ones.

    Fig. S14. Stretching test of the CTFM pixels.

    Fig. S15. Characteristic curves/simulation results of the pseudo-CMOS inverter and a transistor.

    Fig. S16. PSpice simulation and experimental results of the pseudo-CMOS inverter.

    Fig. S17. Effective gain and frequency response of the pseudo-CMOS inverter.

    Fig. S18. Stretching test of the pseudo-CMOS inverter.

    Fig. S19. Demonstration procedures and data storage scheme.

    Fig. S20. Real-time monitoring of amplified ECG signals.

    Table S1. Noise margins of the pseudo-CMOS inverter.

  • Supplementary Materials

    This PDF file includes:

    • Text
    • Fig. S1. Original data corresponding to Fig. 1B.
    • Fig. S2. Fabrication process of the CTFM array.
    • Fig. S3. Fabrication process of the pseudo-CMOS inverter array.
    • Fig. S4. TEM images of AuNP FG assembled using the LB method after the Box deposition using the PEALD process.
    • Fig. S5. TEM-EDS analysis of AuNPs embedded in an FG cell.
    • Fig. S6. Energy band diagrams of CTFM under three representative bias conditions.
    • Fig. S7. EFM images of the FG cell containing different amounts of charges at different locations according to the elapsed time after charge injection.
    • Fig. S8. PGM/ERS characteristics with operation voltages.
    • Fig. S9. PGM/ERS speed analysis of the CTFM array.
    • Fig. S10. Retention characteristics of a CTFM pixel for different memory states.
    • Fig. S11. Retention characteristics of the programmed state (30 V, 0.1 s) and the erased state (−40 V, 0.1 s).
    • Fig. S12. Changes in the transfer curves of a CTFM pixel after repetitive PGM and ERS cycles.
    • Fig. S13. Changes in transfer curves of a CTFM pixel (selected one) after programming or erasing peripheral ones.
    • Fig. S14. Stretching test of the CTFM pixels.
    • Fig. S15. Characteristic curves/simulation results of the pseudo-CMOS inverter and a transistor.
    • Fig. S16. PSpice simulation and experimental results of the pseudo-CMOS inverter.
    • Fig. S17. Effective gain and frequency response of the pseudo-CMOS inverter.
    • Fig. S18. Stretching test of the pseudo-CMOS inverter.
    • Fig. S19. Demonstration procedures and data storage scheme.
    • Fig. S20. Real-time monitoring of amplified ECG signals.
    • Table S1. Noise margins of the pseudo-CMOS inverter.

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