Research ArticleSEMICONDUCTORS

Experimental phase diagram of zero-bias conductance peaks in superconductor/semiconductor nanowire devices

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Science Advances  08 Sep 2017:
Vol. 3, no. 9, e1701476
DOI: 10.1126/sciadv.1701476

Article Information

vol. 3 no. 9

Online ISSN: 
History: 
  • Received for publication May 5, 2017
  • Accepted for publication August 9, 2017

Author Information

  1. Jun Chen1,*,,
  2. Peng Yu1,*,
  3. John Stenger2,
  4. Moïra Hocevar3,
  5. Diana Car4,
  6. Sébastien R. Plissard5,
  7. Erik P. A. M. Bakkers4,6,
  8. Tudor D. Stanescu2, and
  9. Sergey M. Frolov1,§
  1. 1Department of Physics and Astronomy, University of Pittsburgh, Pittsburgh, PA 15260, USA.
  2. 2Department of Physics and Astronomy, West Virginia University, Morgantown, WV 26506, USA.
  3. 3Institut Néel, CNRS, 38042 Grenoble, France.
  4. 4Eindhoven University of Technology, 5600 MB Eindhoven, Netherlands.
  5. 5Centre National de la Recherche Scientifique, LAAS, Université de Toulouse, 31031 Toulouse, France.
  6. 6QuTech and Kavli Institute of Nanoscience, Delft University of Technology, 2628 CJ Delft, Netherlands.
  1. §Corresponding author. Email: frolovsm{at}pitt.edu
    • * These authors contributed equally to this work.

    • Present address: Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA 15261, USA.

    • Present address: Condensed Matter Theory Center and Joint Quantum Institute, Department of Physics, University of Maryland, College Park, MD 20742–4111, USA.

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