Research ArticleAPPLIED PHYSICS

Stable organic thin-film transistors

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Science Advances  12 Jan 2018:
Vol. 4, no. 1, eaao1705
DOI: 10.1126/sciadv.aao1705
  • Fig. 1 General electrical properties and environmental stability.

    (A) The structure of top-gate bottom-contact μc-OTFTs with gate dielectric layers of CYTOP/NL. The semiconductor layers of A_33 and C_33 are TIPS-pentacene/PTAA blend and diF-TES-ADT/PTAA blend, respectively. (B) Transfer characteristics of as-fabricated μc-OTFTs of A_33 (left) and C_33 (right). (C) Electrical parameters of A_33, C_33, and B_44. (D) Environmental stability under continuous dc-bias stress for μc-OTFTs under different ambient conditions.

  • Fig. 2 Operational and temperature stability in N2 during continuous dc-bias stress.

    Temporal evolution of the normalized IDS during dc-bias stress (A) at saturation regime (VDS = VGS = −10 V) for 40 hours with fitted curves and (B) at linear regime (VDS = −2 V, VGS = −10 V) for 100 hours with fitted curves. The insets show the fitting residuals of the SSE model (brown) and the DSE model (green). The |ΔVTH| values after dc-bias stress of as-fabricated A_33 devices (C) at on-state (VDS = VGS = −10 V) and (D) at off-state (VDS = 0 V, VGS = 10 V) bias stress tests under different temperatures in the dark, with curves fitted from corresponding ΔVTH values using the DSE model (see insets).

  • Fig. 3 Long-term stability comparison in different TFT technologies.

    (A) RT measured ΔVTH under on-state bias stress tests of A_33 and C_33 at VDS = VGS = −10 V with fitted curves using a DSE model. (B) Left: RT measured |ΔVTH| under on-state bias stress tests of A_33 and C_33 at VDS = VGS = −10 V with fitted curves from (A). ”*” represents the blue dashed data that are from the state-of-the-art OTFT showing the highest stability by using IDTBT with F4TCNQ molecular additives (19). The orange dashed data are from the sc-organic FET with remarkable stability (14). Right: Comparison between DSE-modeled |ΔVTH| at 55°C for μc-OTFTs and SSE-modeled |ΔVTH| at 50°C for commercial TFT technologies (26).

Supplementary Materials

  • Supplementary material for this article is available at http://advances.sciencemag.org/cgi/content/full/4/1/eaao1705/DC1

    section S1. Electrical properties of μc-OTFTs with different thicknesses of NL

    section S2. Environmental stability

    section S3. One-hour operational stability

    section S4. Long-term operational stability

    section S5. Analytic models of bias stress effects

    section S6. Operational stability of short-channel devices

    section S7. Temperature stability

    section S8. Bias stress effects with different experimental procedures and device bias stress history

    fig. S1. General electrical properties of μc-OTFTs with different configurations of gate dielectric layers.

    fig. S2. Current density–electric field (J-E) characteristics of dielectric layers.

    fig. S3. Environmental stability of μc-OTFTs with different configurations of gate dielectric layers.

    fig. S4. One-hour operational stability of μc-OTFTs.

    fig. S5. One-hour operational stability of μc-OTFTs using a CYTOP/HfO2 dielectric.

    fig. S6. Long-term operational stability of μc-OTFTs.

    fig. S7. Transfer characteristics of μc-OTFTs during long-term operational stability tests.

    fig. S8. Simulation of ΔVTH and the corresponding two opposite contributions of ΔVTH,1 and ΔVTH,2 of μc-OTFTs during dc-bias stress using the DSE model.

    fig. S9. dc-bias stress test of short-channel μc-OTFTs.

    fig. S10. Transfer curves of μc-OTFTs during dc-bias stress at different temperatures.

    fig. S11. Current density–electric field (J-E) characteristics of dielectric layers for A_33 at different temperatures.

    fig. S12. Temporal dynamic of IDS, including interruptions to measure the transfer characteristics, during 47-hour dc-bias stress at VDS = VGS = −10 V at RT.

    fig. S13. VTH shifts of A_33 and C_33 devices that were tested after long-term operational and environmental stability tests.

    table S1. Summary of the device properties and pristine electrical performance.

    table S2. Summary of the device electrical parameters before and after stress tests.

    table S3. Summary of lifetime parameters of TFTs using the SSE model.

    table S4. Summary of lifetime parameters of μc-OTFTs using the DSE model.

    table S5. Summary of μc-OTFTs lifetime parameters at different temperatures using the DSE model.

    table S6. Summary of lifetime parameters of μc-OTFTs extracted from VTH shifts using the DSE model.

    References (33, 34)

  • Supplementary Materials

    This PDF file includes:

    • section S1. Electrical properties of μc-OTFTs with different thicknesses of NL
    • section S2. Environmental stability
    • section S3. One-hour operational stability
    • section S4. Long-term operational stability
    • section S5. Analytic models of bias stress effects
    • section S6. Operational stability of short-channel devices
    • section S7. Temperature stability
    • section S8. Bias stress effects with different experimental procedures and device bias stress history
    • fig. S1. General electrical properties of μc-OTFTs with different configurations of gate dielectric layers.
    • fig. S2. Current density–electric field (J-E) characteristics of dielectric layers.
    • fig. S3. Environmental stability of μc-OTFTs with different configurations of gate dielectric layers.
    • fig. S4. One-hour operational stability of μc-OTFTs.
    • fig. S5. One-hour operational stability of μc-OTFTs using a CYTOP/HfO2 dielectric.
    • fig. S6. Long-term operational stability of μc-OTFTs.
    • fig. S7. Transfer characteristics of μc-OTFTs during long-term operational stability tests.
    • fig. S8. Simulation of ΔVTH and the corresponding two opposite contributions of ΔVTH,1 and ΔVTH,2 of μc-OTFTs during dc-bias stress using the DSE model.
    • fig. S9. dc-bias stress test of short-channel μc-OTFTs.
    • fig. S10. Transfer curves of μc-OTFTs during dc-bias stress at different temperatures.
    • fig. S11. Current density–electric field (J-E) characteristics of dielectric layers for A_33 at different temperatures.
    • fig. S12. Temporal dynamic of IDS, including interruptions to measure the transfer characteristics, during 47-hour dc-bias stress at VDS = VGS = −10 V at RT.
    • fig. S13. VTH shifts of A_33 and C_33 devices that were tested after long-term operational and environmental stability tests.
    • table S1. Summary of the device properties and pristine electrical performance.
    • table S2. Summary of the device electrical parameters before and after stress tests.
    • table S3. Summary of lifetime parameters of TFTs using the SSE model.
    • table S4. Summary of lifetime parameters of μc-OTFTs using the DSE model.
    • table S5. Summary of μc-OTFTs lifetime parameters at different temperatures using the DSE model.
    • table S6. Summary of lifetime parameters of μc-OTFTs extracted from VTH shifts using the DSE model.
    • References (33, 34)

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