Research ArticleAPPLIED SCIENCES AND ENGINEERING

Thermionic junction devices utilizing phonon blocking

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Science Advances  10 Apr 2020:
Vol. 6, no. 15, eaax9191
DOI: 10.1126/sciadv.aax9191
  • Fig. 1 Cooling scheme.

    (A) Conceptual image of particle fluxes through solid-state thermionic barrier/interface connecting hot and cold reservoirs. The interface suppresses phonon heat flow between the reservoirs and acts as a thermionic junction that governs electron transport. (B and C) Electron (B) and phonon (C) interfaces between the reservoirs. Electron transport is limited by the energy gap of the superconducting lead and phonon transport by the phonon thermal boundary resistance RPTB. (D) Simplified heat resistance network of our system presenting the electric heat flow/power (PSmS) of the Sm-S junctions and the thermal resistance between the hot and cold reservoirs (Rph), which depends on RPTB and lead thermal resistance (Rlead). For a more detailed version, see fig. S7. (E) Artistic image of the experimental cooling platform. The subchip is physically supported by 24 Sm-S junctions connected to the aluminum leads, which mediate the heat conduction between the main chip and subchip. The large size of the subchip ensures that its electrons and phonons share the same temperature. (F) Scanning electron micrograph of a sample with Ø 1-mm subchip. One pair of Sm-S junctions is biased with alternating current (ac) and used as a thermometer, whereas one or more of the other pairs are biased with direct current (dc) and used as heaters or coolers. The measurement setup is further discussed in Materials and Methods, sections S1 and S2, and fig. S1. (G and H) SEM images of the cross section of a tunnel junction (G) and two superconducting leads (H), showing that the superconducting leads are mechanically connected to the subchip only via the Sm-S tunnel junctions (indicated by white arrow), with diameters between 1.5 and 3 μm.

  • Fig. 2 Measurement results.

    (A) Relative difference between the subchip temperature T2 and bath temperature T1 for samples S1, S2, and S3 at optimal cooling voltage with 22, 20, and 22 cooler junctions, respectively. The largest absolute temperature reduction is indicated by arrows. Refrigeration is modeled by setting the heat leak (T−3 fits of B) in balance with the cooling power produced by ideal Sm-S junctions (dashed curves) or by Sm-S junctions that have finite subgap leakage (solid curves). (B) Thermal resistance between the subchip and its environment for samples S1, S2, and S3, and T−3 fits (solid lines). Error margins are dominated by the uncertainty of simulation parameters and by measurement uncertainty (see section S8 for details).

  • Fig. 3 Future prospects.

    (A and B) The achievable relative temperature reduction with any superconductor with critical temperature Tc when γ = 10−3. The horizontal lines are calculated with RA = 100 Ωμm2. (A) Cooling against RPTB. The y axis is normalized with Lorentz number, L0. Black horizontal lines show values for aluminum-based (Tc, Al = 1.184 K) and vanadium-based (Tc, V = 5.38 K) junctions, when parameters of S3 are used for Rph, and correspond to the solid lines in (C). (B) Constriction-limited cooling as a function of NRT, where N is the effective number of thermal conductance quanta in the constriction, and it incorporates the possible effects of scattering/low transmission (i.e., N can be even below unity). The black horizontal line corresponds to the dotted lines in (C) and is calculated when N equals 10 quanta per tunnel resistance of RT = 100 ohms. (C) Refrigeration efficiency of aluminum-based (red), vanadium-based (blue), and their cascade-based (cyan) coolers as a function of temperature. The tunnel junction parameters are as in (A) and (B). In the cascade, vanadium-silicon junctions (having much higher optimal cooling temperature than Al-Si junctions) are used to refrigerate aluminum down to a temperature at which Al-Si junctions operate effectively, and Al-Si junctions refrigerate the actual payload to the minimum temperature. The solid lines indicate a case where Rph is the same as in S3. The dashed lines present a situation where Rph is increased by factor 10, and the dotted lines present the temperature reduction when RPTB is as in S3, but Rlead is increased by the constriction as in (B). (D) Artistic image of a cascaded cooler.

  • Table 1 Sample parameters and literature values for thermal boundary resistance.

    Here, A is the area of a tunnel junction, d is the diameter of the subchip, RA = RTA is the characteristic junction resistance, and RT is the junction resistance. Thermal resistance prefactors (α) are the values obtained from the fits of Fig. 2, whereas αAMM and αDMM correspond to theoretical RPTB (35).

    SampleA
    μm2
    d
    μm
    RA = RTA
    Ωμm2
    α
    K4/μW
    αAMM
    K4/μW
    αDMM
    K4/μW
    Max cooling
    %
    Max cooling
    mK
    S12.0/137*3005384.515 (@ 140 mK)22 (@ 166 mK)
    S27.510004765.66.58.840 (@ 170 mK)83 (@ 244 mK)
    S33.2300194529162129 (@ 173 mK)56 (@ 220 mK)

    *Sample S1 had silicon oxide between leads and subchip, and therefore, the effective area of the phononic heat contact, 137 μm2, is larger than the junction area 2.0 μm2.

    Supplementary Materials

    • Supplementary Materials

      Thermionic junction devices utilizing phonon blocking

      Emma Mykkänen, Janne S. Lehtinen, Leif Grönberg, Andrey Shchepetov, Andrey V. Timofeev, David Gunnarsson, Antti Kemppinen, Antti J. Manninen, Mika Prunnila

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      This PDF file includes:

      • Sections S1 to S10
      • Figs. S1 to S11
      • Tables S1 to S3
      • References

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