Nanoparticle-based computing architecture for nanoparticle neural networks

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Science Advances  26 Aug 2020:
Vol. 6, no. 35, eabb3348
DOI: 10.1126/sciadv.abb3348
  • Fig. 1 NVNA on an LNT chip.

    (A) Schematic of NVNA-LNT. The LNT is operated with software composed of Instruction DNAs in solution and hardware composed of nanoparticles on a lipid bilayer. The hardware consists of a data storage unit, NM; an output unit, NR; and a processing unit, NF. A set of Instruction DNAs programs logic operation using a kinetic difference between nanoparticle reactions with memory storage state. (B) LNT protocol: (i) data storage on NM, (ii) neural network (NNN) operation by Instruction DNA set addition, and (iii) reset by dehybridizing DNAs for the next executions. (C) Time-lapse dark-field microscopic imaging can differentiate each nanoparticle on LNT via scattering color and mobility. The nonlabeled nanoparticles are NM. (D) Molecular information storage on the NM changes the exposed single-stranded domain. (E) YES gate operation results. Input “1” results in output “1,” printing the NF-NR. Otherwise, all NFs are trapped to NM and exhibit no reaction on NR, which is output “0.”

  • Fig. 2 Software programming strategy using Instruction DNAs.

    (A) Reaction kinetics of three types of Instruction DNAs. The addition of 8 nM NM0 and NM1 Trap DNAs allows fast logic-allowed trapping (solid lines) of NFs to NM with the “0” and “1” states, respectively, and no or slow logic-forbidden binding (dotted lines). The 1 nM Report DNA addition shows binding of NFs to NRs with a lag time. (B) Programming of NOT gate from an If-Then-Else statement to a combination of Instruction DNAs coding the NNN. (C) NOT gate operation in the LNT. For input “0,” the NF has no specific interaction with M0 and generates NF—NR assemblies (cyan dotted circle) as the output “1” (reporting ratio > 0.2, green box). For DNA input “1” stored in the NM, the NFs are trapped to the NM1 (yellow dotted circle), resulting in the output “0” (reporting ratio = < 0.2, green box).

  • Fig. 3 Programming a two-input Boolean logic gate with NNN and demonstration of a reset function.

    (A) Single-layer perceptron for an AND logic gate. The nanoparticle network at four input combinations is represented with the solid lines indicating the nanoparticle assembly reaction and the dotted lines indicating no or a suppressed reaction. The output “1” (blue box) is represented by NF—NR reporting (blue dots) to NF—NM trapping (green dots) over 0.2 (green box). (B) Multiple executions of logic gates in a single chip by resetting after each execution (yellow box). (C) Execution of INH and NOR logic gates using weight coding. (D) Execution of OR, NAND, XOR, and XNOR logic gates using multilayer perceptron with two types of NF. The output “1” is represented by a reporting ratio between 0.2 and 0.6 because a single NF between two NFs generates the output “1.”

  • Fig. 4 Execution of a 2-bit comparator with decision tree on a single chip.

    (A) Digital logic circuit and NNN diagram for AB > CD, and operation result of 16 combinations of two 2-bit input AB and CD. (B) Decision trees for the magnitude comparator. The two-layered tree structure generates three results, indicating the relative magnitude of two 2-bit binary inputs. Four-bit inputs of 1111, 0110, and 1000 result in AB = CD, AB < CD, and AB > CD, respectively. Scale bars, 1 μm.

Supplementary Materials

  • Supplementary Materials

    Nanoparticle-based computing architecture for nanoparticle neural networks

    Sungi Kim, Namjun Kim, Jinyoung Seo, Jeong-Eun Park, Eun Ho Song, So Young Choi, Ji Eun Kim, Seungsang Cha, Ha H. Park, Jwa-Min Nam

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