CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

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Science Advances  13 Jan 2021:
Vol. 7, no. 3, eabe1341
DOI: 10.1126/sciadv.abe1341


Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high processing temperature, non-CMOS compatibility, difficulty in scaling, and complex compositions of perovskite oxides. Here, we demonstrate a unique strategy to tackle critical issues by applying hafnia-based ferroelectrics and oxide semiconductors. Thus, it is possible to avoid the formation of interfacial layer that finally allows unprecedented Si-free 3D integration of ferroelectric memory. This strategy yields memory performance that could be achieved neither by the conventional flash memory nor by the previous perovskite ferroelectric memories. Device simulation confirms that this strategy can realize ultrahigh-density 3D memory integration.


Current flash memory devices used in massive data storage for mobile devices and servers are based on floating-gate or charge-trap memory transistors using electron tunneling through a tunnel oxide (1, 2). As the electron-tunneling process requires voltage pulses with high amplitude and long duration, current flash memory devices usually require high operation voltage of ~20 V and slow speed of ~10−3 s and show limited endurance of ~104 cycles (35). In addition, it requires high deposition (>600°C) and/or annealing (>900°C) temperatures to form channel and oxide layers (6, 7). To overcome these limitations, many types of emerging memory devices have been evaluated, but still, there have been no alternatives to current flash memory (810). A ferroelectric memory transistor can be a viable candidate to replace current flash memory because of its potential to obtain fast operation at a low power (11, 12). In a ferroelectric memory transistor, the charges in the channel layer can be directly controlled by the polarization of a ferroelectric layer that is incorporated into the gate stack of the ferroelectric transistor (13). Although previous studies that use ferroelectric perovskite oxides deposited on Si wafers show the feasibility as high-performance flash memory applications, formation of an interfacial layer with a Si channel imposes limits of memory window, endurance, and data retention properties (1417). In addition, the complex compositions of perovskite oxides limit the applicability of ferroelectric memory as next-generation flash memory devices (18, 19). Furthermore, three-dimensional (3D) integration of such ferroelectric memories is a key requirement for commercialization but has been unattainable because deposition of perovskite oxides and noble metals in 3D structures is a difficult task and those materials are very difficult to etch (19).

Hafnia-based ferroelectric materials have gained research interest because of their potential to have complementary metal-oxide semiconductor (CMOS) compatibility, low power consumption, and fast switching speed (19). In addition, recent studies suggested that hafnia-based ferroelectrics could be scaled down to <1 nm while maintaining ferroelectricity (20). Because of these advantages, hafnia-based ferroelectric materials have been adopted in ferroelectric memory transistors, negative-capacitance field-effect transistors (FETs), ferroelectric tunneling junctions, and artificial synapses (2126). Hafnia-based ferroelectric materials can be deposited conformally on the vertical structures using atomic layer deposition (ALD), so ferroelectric transistors that use them are regarded as promising candidates for use in 3D memory such as 3D NAND (27, 28). However, device performance issues derived from the formation of an interfacial layer with a Si channel still need to be solved (29).

Here, we present unique integration strategies to overcome the aforementioned key issues in ferroelectric memory transistors by introducing indium zinc oxide (InZnOx) as the semiconductor layer and zirconium-doped hafnium oxide (HfZrOx) as the ferroelectric layer. First, SiOx interfacial layer inherently unavoidable from the conventional perovskite oxide– or hafnia-based ferroelectric memories on Si could be effectively prevented by using InZnOx as a semiconductor while maintaining necessary material qualities (or comparable materials quality as that of Si) to obtain high-performance memories. This results in several hundreds of times faster operation speed (<10−6 s) and four times lower operation voltage (<5 V) compared to current flash memory (3, 30). In addition, the absence of an interfacial layer allows outstanding endurance characteristics (>108 cycles) of ferroelectric transistors compared to both charge-trap flash memory (~104) and ferroelectric transistor with a Si channel (~107) (5, 23, 29, 31). As all processes can be done below 400°C, the integrated ferroelectric memory devices are CMOS compatible such that we are able to confirm that our process can achieve commercialization milestones including demonstration of NAND flash arrays and 3D vertical structures. Our nanoscale 3D vertical flash memory exhibits excellent performances that promise ultrahigh-density 3D flash memory in the future. The 3D device shows a large memory window of 2.5 V and stable switching characteristics for 108 cycles. Device simulation confirms the operation mechanism and possibility of ultrahigh-density 3D memory integration. These results demonstrate the plausibility of ALD-based ferroelectric memory as future 3D nonvolatile memory devices such as 3D vertical NAND.


Combination of hafnia-based ferroelectrics and oxide semiconductor for high-performance ferroelectric transistor

To confirm ferroelectric properties of HfZrOx, we fabricated a capacitor that had a TiN/HfZrOx/TiN structure and measured the polarization–electric field (P-E) characteristics of 24-nm-thick HfZrOx (fig. S1A). HfZrOx showed a positive remnant polarization of +Pr = 15.1 μC/cm2 and a negative remnant polarization of −Pr = −13.8 μC/cm2. The coercive electric field of HfZrOx was ~1.2 MV/cm; this is larger than those of ferroelectric perovskite oxides (~0.05 MV/cm) and can be advantageous in ferroelectric transistor because large coercive electric field can lead to a large memory window (18). Therefore, a sufficient memory window can be achieved using a thin HfZrOx layer compared to perovskite oxides. The ferroelectricity of HfZrOx was also confirmed using piezoresponse force microscopy (PFM) and capacitance-voltage (C-V) measurements. The PFM amplitude and phase images were measured after applying −6 V to the outer square region and then with +6 V to the inner square region of the sample. The clear difference in contrast showed different polarization states of HfZrOx in PFM amplitude (fig. S1B) and phase images (fig. S1C). The C-V curve exhibited butterfly-shaped hysteresis, which is a result of the ferroelectric property of HfZrOx (fig. S1D). These results confirmed the ferroelectric nature of HfZrOx film. The endurance and polarization switching characteristics of HfZrOx were characterized. For endurance characteristics, repeated voltage pulses with an amplitude of ±6 V and a width of 5 μs were applied (fig. S1E). The ferroelectric HfZrOx showed stable switching characteristics for 108 cycles. The polarization switching characteristics of the HfZrOx were evaluated by measuring switching and nonswitching polarization characteristics under application of voltage pulses with an amplitude of 7.2 V (i.e., 3 MV/cm) and different widths (fig. S1F). As a pulse width was increased from 30 to 700 ns, the switched polarization of HfZrOx increased.

To investigate the feasibility of our integration strategies, ferroelectric thin-film transistors (FeTFTs) with a bottom-contact structure were fabricated by combining ALD-based HfZrOx and InZnOx (Fig. 1A). Their electrical characteristics were quantified by sweeping gate voltage VG between −5 and 5 V at source-drain voltages VDS of 0.1, 0.05, and 0.01 V. The FeTFT showed counterclockwise hysteresis, which originated from ferroelectric polarization switching in the HfZrOx (Fig. 1B). The linear field-effect mobility of InZnOx channel in FeTFTs was ~1.9 cm2 V−1 s−1, which is lower than that of InZnOx on the SiO2 layer (~7.8 cm2 V−1 s−1). This difference seems to originate from the high dielectric constant of the HfZrOx layer, which can induce remote phonon scattering (32). This remote phonon scattering can be reduced by using gate electrode layers with a high electron density (33, 34). In addition, the mobility of InZnOx channel can be further increased by optimizing process parameters, such as doping and growth temperature (35). To quantify the memory window of the FeTFT, the device was programmed and erased by applying positive (5 V, 10 ms) and negative (−5 V, 10 ms) VG pulses, respectively. After each pulse had been applied, VG was swept from 0 to −5 V to verify the state of devices. The threshold voltages Vth of programmed and erased states were extracted using linear extrapolation (Fig. 1C) (36). The memory window, which is the difference between Vth of programmed and erased states, was larger in our FeTFT (>2 V) than previously reported FeTFTs with hafnia-based ferroelectric materials and oxide semiconductors (0.5 to 1 V) (21, 22). To determine the switching characteristics of FeTFT based on HfZrOx and InZnOx, the VG pulses with different amplitudes and widths were applied. Before measurement, FeTFTs were erased by applying a negative VG pulse (−5 V, 10 ms). Then, pulses with a width of 1 μs and amplitudes of 3 to 5 V in increments of 0.2 V were applied. As the amplitudes of pulses were increased, the Vth of the device was changed (Fig. 1D). A memory window of ~2 V could be achieved using a pulse that had an amplitude of 5 V, which is about four times lower than the pulse amplitude required for conventional flash memory (37, 38). Vth change was also observed as pulse widths were increased from 100 ns to 1 μs at an amplitude of 5 V (Fig. 1E). These switching characteristics may be a result of partial polarization switching of the HfZrOx layer, which can be controlled by the condition of applied pulses (39, 40). A memory window of ~1 V could be achieved using a voltage pulse width of 500 ns, which was about several hundreds times faster than the erase operation speed of conventional flash memory for acquiring a similar memory window (30, 41). The memory window of flash memory is dependent on memory operations, such as multilevel data storage, and flash memory can be operated faster when a small memory window is required (42). However, still much higher program/erase voltages are required, compared to the ferroelectric memory presented in this study (30). To confirm the reliability of FeTFT based on HfZrOx and InZnOx, we investigated the endurance properties using devices with different memory windows of 0.5 and 1.5 V. Memory windows of 0.5 and 1.5 V were obtained by applying triangular pulses (5 V, −7 V) and (6 V, −8 V), respectively (Fig. 1F and fig. S2). The pulse width of 500 ns and 1 μs was used for program and erase operation, respectively. After consecutive program and erase pulses had been applied, the device states were confirmed by sweeping VG from 0 to −5 V. With a memory window of 0.5 V, FeTFT using ALD-based HfZrOx and InZnOx showed stable switching characteristics for 108 cycles. The robust endurance characteristics of ALD-based FeTFTs seem to originate from its metal-ferroelectric-semiconductor structure without interfacial layer (29). When a Si layer is used as a channel, SiOx interfacial layer can be formed between the channel and ferroelectric layer, so ferroelectric transistors with a Si channel have a metal-ferroelectric-insulator-semiconductor (MFIS) structure (31, 43, 44). When VG is applied to the MFIS structure, much of the applied electric field can be induced in SiOx interfacial layer because of its low dielectric constant compared to the ferroelectric layer. The high electric field in SiOx interfacial layer can cause charge tunneling across the SiOx interfacial layer and induce charge trapping in the ferroelectric layer; it can degrade endurance characteristics (29, 31). In our FeTFTs, the formation of an interfacial layer can be suppressed by using an oxide semiconductor channel; the absence of an interfacial layer yielded stable endurance characteristics. In addition, a comparison was made between this work and previous memory devices such as charge-trap memory, perovskite oxide–based ferroelectric transistors, and hafnia-based ferroelectric transistors (table S1) (12, 23, 29, 31, 4551). The use of HfZrOx and InZnOx resulted in lower operation voltage, faster operation speed, and lower processing temperature compared to conventional charge-trap memory and perovskite oxide–based ferroelectric transistor. In addition, by avoiding the formation of the SiOx interfacial layer, robust endurance characteristics were achieved compared to charge-trap memory and ferroelectric transistors.

Fig. 1 FeTFT for nonvolatile memory applications.

(A) Schematic illustration of FeTFT that uses HfZrOx and InZnOx. (B) Transfer curves of FeTFT with VDS = 0.1, 0.05, and 0.01 V. (C) IDS-VG curves of FeTFT in erased and programmed states. Threshold voltage Vth is extracted using the linear extrapolation. A memory window is the difference between erased and programmed Vth of FeTFT. Vth change of FeTFT according to (D) amplitudes and (E) widths of program pulses. In operation with different pulse amplitudes, pulse amplitudes are increased from 3 to 5 V and a width is fixed at 1 μs. In operation with different pulse widths, pulse widths are increased from 100 ns to 1 μs and an amplitude is fixed at 5 V. (F) Endurance characteristics of FeTFT for 108 cycles using positive (5 V, 500 ns) and negative (−7 V, 1 μs) triangular pulses for program and erase operations, respectively.

Memory operation of integrated ferroelectric NAND

The structure of a ferroelectric NAND (FeNAND) flash memory array is analogous to that of NAND flash devices (fig. S3A). The difference is the type of memory cell; FeNAND uses ferroelectric transistors, whereas NAND flash uses conventional flash memory. In FeNAND, a page consists of ferroelectric transistor memory cells that share a word line (WL). An FeNAND string includes ferroelectric transistor memory cells connected in series. All of the FeNAND strings share a source line (SL). Each NAND string is connected to bit lines (BLs) (12, 52). We fabricated a 4 × 4 FeNAND array by integrating FeTFTs with a ferroelectric HfZrOx layer and an InZnOx channel layer (fig. S3B). The fabrication process of FeNAND was CMOS compatible and could be done below 400°C. First, TiN was deposited for WLs on the SiO2/Si substrate, and HfZrOx layer was deposited for the ferroelectric layer. A Mo layer was deposited for BL/SL, and an InZnOx layer was deposited for the channel layer. ALD was used to deposit the HfZrOx and InZnOx layers. The annealing process to induce the ferroelectric phase in the HfZrOx layer was performed at 400°C after deposition of the InZnOx layer. The processing temperature of FeNAND is lower than that of ferroelectric devices based on perovskite oxides (>700°C) (12, 48, 49). Last, etching process was done to open the contacts for WLs. The fabricated 4 × 4 FeNAND array was composed of four WLs (WLn; n = 0, 1, 2, and 3) and four NAND strings (Fig. 2A). Each NAND string was connected to BLs (BLm; m = 0, 1, 2, and 3). All NAND strings were connected to the same SL. In this 4 × 4 FeNAND array, each of the 16 memory cells Cnm was positioned on the cross-point of WLn and NAND strings on BLm. This array was used to demonstrate program operation of FeNAND. In a NAND structure, an unwanted programming may occur in memory cells that share a WL with the selected memory cell during program operation; this phenomenon is called program disturbance (12, 52). To avoid program disturbance, the program-inhibit operation method was used. As an example, memory cells of C20 and C21 were selected as programmed and program-inhibited cells, respectively. Before program operation, FeTFT memory cells in FeNAND array were erased by applying an erase pulse with an amplitude of VE = −5 V and a width of 10 ms to WL2, while 0 V was applied to the BLs and SL (Fig. 2B). Then, to program C20, a program pulse with an amplitude of VP = 5 V and a width of 10 ms was applied to the selected WL2, and 0 V was applied to the BL0. To inhibit the program of C21 that shared the WL2 with C20, program-inhibit pulses with an amplitude of Vinhibit = 2.5 V and a width of 30 ms were applied to BL1 and SL (Fig. 2C). Pass voltage with an amplitude of Vpass = 2.5 V and a width of 30 ms was applied to unselected WLs. Vpass can also disturb the states of the memory cell. Therefore, the effect of Vpass on pass disturbance was investigated by increasing the amplitude of Vpass from 0.5 to 4 V. In the range of Vpass > 3 V, pass disturbance occurred, so Vpass with an amplitude of 2.5 V was used for program-inhibit operation (fig. S4). After erase and program operations, the states of memory cells were confirmed by applying WL voltage VWL sweep (0 → −5 V) to the selected WL2. During these operations, only the memory cell C20 could be programmed by the difference in voltage between the gate and channel layer (53). Otherwise, the program could be inhibited by program-inhibit operation in the program-inhibited cell C21. While Vinhibit was applied to BL1 and SL, the channel potential could be increased; the difference in voltage between gate and channel could be decreased to VPVinhibit (5254). The program of C21 was prevented by program-inhibit operation method using Vinhibit = 2.5 V because polarization switching of HfZrOx layer in C21 was hindered (Fig. 2D). These results indicated that the difference in voltage between gate and channel was small enough to avoid erroneous program of C21. To investigate how program-inhibit pulses affect the program-inhibited cell, the program operation was performed using program-inhibit pulses with different amplitudes (fig. S5). The amplitudes of program-inhibit pulses were increased from 0 to 2.5 V in increments of 0.5 V. The program-inhibit behaviors depended on the amplitudes of Vinhibit. At Vinhibit < 1 V, the unwanted program of memory cell C21 (unwanted cell) happened. As the amplitude of Vinhibit was increased, program of memory cell C21 was inhibited (53). Program-inhibit operation using Vinhibit = 2.5 V could successfully prevent unwanted program; this was confirmed by repeated program and program-inhibit operations (fig. S6). These results indicated that program disturbance could be effectively reduced by applying Vinhibit.

Fig. 2 Operation characteristics of FeNAND.

(A) Optical image of 4 × 4 FeNAND flash memory array (left) and NAND strings in FeNAND flash memory array including programmed cell (C20) and program-inhibited cell (C21) (right). (B and C) Equivalent circuits of FeNAND flash memory array and erase/program operations. VP, VE, Vpass, and Vinhibit stand for program, erase, pass, and inhibit voltages, respectively. (D) IBL-VWL curves of C20 memory cell and C21 memory cell after erase and program operations. Program of C21 memory cell is prevented by program-inhibit operation. Program-inhibit pulse with an amplitude of Vinhibit = 2.5 V is used for program-inhibit operation. During program-inhibit operation, the channel potential of C21 memory cell could be boosted to Vinhibit.

All 16 memory cells in FeNAND array were operated without any failures. The states of memory cells were confirmed by measuring IBL-VWL curves of programmed and erased states (Fig. 3A). Memory cells showed a clear separation in IBL-VWL curves after program and erase operations. The device states could be confirmed nondestructively by measuring the string current while the read voltage VR was applied to the selected cell. For nondestructive read operation, the amplitude of VR was chosen within a range that did not induce switching of the polarization state in the ferroelectric layer. During application of VR with an amplitude of −2 V, the states of the memory cells did not change. Therefore, to read the state of the selected memory cell, VR = −2 V was applied to the selected WL while BL read voltage VRBL was swept from 0 to 0.5 V. By measuring readout current Ireadout of memory cell, the polarization state of ferroelectric layer in the selected memory cell was confirmed. Ireadout of the 16 memory cells in the 4 × 4 FeNAND array was measured in programmed and erased states (fig. S7). Ireadout showed clear difference according to memory states (Fig. 3B). The string- and page-level NAND operations were demonstrated using the FeNAND device. Three different cases of NAND strings (all programmed cells, one erased and all other programmed cells, and all erased cells) were used (Fig. 3C). Ireadout of a string was measured while VR = −2 V was applied to all WLs. When all memory cells were programmed, the NAND string was on state. However, when the string included at least one erased cell, the NAND string was off state because all memory cells in a string were connected in series (Fig. 3D). These results confirmed that NAND memory operation is possible using an array of FeTFTs.

Fig. 3 Memory operation of FeNAND.

(A) IBL-VWL of 16 memory cells in programmed and erased states. (B) Statistical distribution of readout current Ireadout of 16 memory cells in programmed (blue) and erased (red) states. (C) NAND operations: All programmed cells (case 1), one erased and all other programmed cells (case 2), and all erased cells (case 3). (D) Ireadout of NAND strings in cases 1, 2, and 3. Only the memory string that has all programmed cells shows the on state; when even one cell is erased, the off state is obtained.

To investigate the wafer-scale uniformity of devices, we fabricated FeNAND arrays on the 4-inch SiO2/Si wafer (fig. S8A). Program and erase operations of nine memory cells from different positions on the wafer were measured (fig. S8B). Memory cells in programmed and erased states showed clear differences in Ireadout (fig. S8C). These results indicated that FeNAND fabricated using ALD could exhibit uniform electrical characteristics on the wafer scale. Using a program pulse with different amplitudes, Vth tuning characteristics of memory cell in FeNAND were demonstrated (fig. S9A). First, the memory cell was erased by applying an erase pulse (−5 V, 10 ms). Then, program pulses with amplitudes of 3.3, 3.8, and 5 V were applied. As the amplitude of program pulses was increased, IBL-VWL curves were shifted to the negative direction. Memory cells in FeNAND showed Vth of four different states for repeated cycles using program pulses with different amplitudes (fig. S9B).

Nanoscale vertical FeTFTs for high-density ferroelectric memory

To confirm the feasibility of FeTFTs as a 3D memory device, we fabricated a vertical FeTFT array by sequentially depositing a 50-nm-thick SiO2 insulator and 100-nm-thick TiN gate electrodes (Fig. 4, A and B). As HfZrOx and InZnOx layers were deposited using ALD, both layers were conformally deposited (Fig. 4C). Here, we defined the FeTFT using the middle TiN gate electrode positioned between the SiO2 layers as middle TFT (m-TFT). The effective channel area of the m-TFT was 10 μm2 (channel length/width, 100 nm/100 μm). The electrical characteristics of m-TFT were investigated by applying VG sweep to the m-TFT gate electrode at VDS = 1 V, while applying Vpass of 1 V to the unselected gate (i.e., top and bottom TiN) electrodes (Fig. 4D). An n-type transfer characteristic with counterclockwise hysteresis was observed when VG sweep of −5 → 5 → −5 V was applied to the m-TFT gate electrode. The memory window of vertical FeTFT was about 2.5 V. This result implies that the FeTFTs can be operated in a vertically stacked structure with a channel length of 100 nm. The switching characteristics of the m-TFT were verified by applying voltage pulses with different pulse widths and amplitudes (Fig. 4E). The required pulse width for program operation was decreased as the amplitude of voltage pulse increased. To confirm the reliability of m-TFT, the endurance properties were investigated by applying positive (6 V, 1 μs) and negative (−7 V, 1 μs) triangular pulses as program and erase pulses, respectively (Fig. 4F). After consecutive program and erase pulses had been applied, the device states were confirmed by sweeping VG from 0 to −3 V. m-TFT showed stable switching characteristics for 108 cycles. In addition, similar transfer characteristic with counterclockwise hysteresis was observed in m-TFT device with the effective channel area of 0.2 μm2 (length/width, 20 nm/10 μm). These results indicate that fabrication processes using our integration strategies are compatible with 3D structured devices with a large memory window and excellent endurance characteristics.

Fig. 4 Nanoscale vertical FeTFT array.

(A) Fabrication process flow for vertical FeTFT array. (B) Optical image of the vertical FeTFT device array. S and D stand for source and drain, respectively. (C) Cross-sectional scanning electron microscope image (false colors) of the vertical FeTFT array. (D) Transfer curve of m-TFT with counterclockwise hysteresis. For characterization, VG sweep is applied to m-TFT gate electrode, while Vpass = 1 V is applied to unselected gate electrodes. (E) Vth change of m-TFT device according to program pulse amplitudes and widths. (F) Endurance characteristics of m-TFT device for 108 cycles using positive (6 V, 1 μs) and negative (−7 V, 1 μs) triangular pulses for program and erase operations, respectively.

We simulated the vertical FeTFT array using Technology Computer-Aided Design (TCAD) tool (Fig. 5A). Before FeTFT simulation, we first simulated P-E characteristics of a ferroelectric capacitor using 24-nm-thick HfZrOx and compared with experimental results (fig. S10) (55, 56). TiN was used for both top and bottom electrodes; saturation polarization, remnant polarization, coercive electric field, and Landau-Khalatnikov parameters of the HfZrOx were extracted from the experimental data (55, 57). The simulated P-E hysteresis was similar to the experimental result, which indicated that the ferroelectric characteristics could be properly simulated using the TCAD tool. The materials and their thicknesses were set by reference to the experimental results (Fig. 5B). Positive (5 V, 100 μs) and negative (−5 V, 100 μs) pulses were applied to the m-TFT gate electrode (i.e., selected cell) for program and erase operation while applying Vpass = 1 V to unselected gate electrodes. The polarization in HfZrOx layer was clearly changed after program and erase operation (Fig. 5, C and D). Last, VG sweep from −3.5 to 2 V was applied to fabricated and simulated vertical FeTFT arrays after program and erase operation (Fig. 5E). Experimental and simulated results showed similar program and erase characteristics. The results confirmed that the electrical characteristics and operation of FeTFTs could be properly simulated using the TCAD tool.

Fig. 5 Device simulation of vertical FeTFT array.

(A) Device structure of simulated vertical FeTFT array. (B) Materials and their thicknesses used for simulation. (C) Magnified image of the vertical FeTFT array. (D) Simulated polarization in HfZrOx layer at programmed and erased states. For program and erase operations, voltage pulses (5 V, 100 μs) and (−5 V, 100 μs) are applied to the m-TFT gate, respectively. Polarization in the HfZrOx layer is clearly changed after program and erase operations. (E) Experimental and simulated IDS-VG curves of the m-TFT at programmed and erased state.

Device simulation of 3D FeNAND

To estimate the feasibility of FeTFTs based on HfZrOx and InZnOx in future 3D FeNAND, we simulated a single string that contained 16 WLs, a string select line, and a ground select line (Fig. 6A) (58, 59). The single string of 3D FeNAND was fabricated using the gate-last process, which is similar to terabit cell array transistors (fig. S11) (5, 60). First, nitride and oxide layers were sequentially deposited on the p-type (100) Si substrate in which n-well, p-well, and source were formed by implantation of phosphorous of 1013 cm−3, boron of 1013 cm−3, and arsenic of 1016 cm−3, respectively. A channel hole with a radius of 80 nm was etched; a 10-nm-thick oxide semiconductor channel was deposited, and the channel hole was filled with SiO2 (i.e., filler material). Nitride layers were etched, and 24-nm-thick HfZrOx was deposited. Last, TiN WLs and Mo BLs were deposited. In our suggested 3D FeNAND, 30-nm-thick TiN, 24-nm-thick HfZrOx, 10-nm-thick InZnOx, and Mo were used as WL, ferroelectric gate insulator, oxide semiconductor channel, and BL, respectively, and the thickness of the SiO2 spacer between adjacent WLs was 30 nm. To observe the operation characteristics of the 3D FeNAND, block-erase and program operations were performed (Fig. 6, B and C). First, all WLs were block-erased by applying a voltage pulse (10 V, 10 μs) to the substrate. Then, WL11 and WL13 cells were sequentially programmed by applying a voltage pulse (4 V, 1 μs) to the selected WLs. After programming WL11 and WL13 cells, WL12 cell was programmed using the same method. The polarization in the HfZrOx layer was clearly changed after block-erase and program operations. In addition, the polarization state in WL12 was not changed after programming WL11 and WL13; this result indicated that adjacent cells caused no noticeable disturbance. Last, VWL sweep from −3 to 1 V was done to WL12 after block-erase and program operations (Fig. 6D). The IBL-VWL characteristics of WL12 were not changed after programming adjacent cells (i.e., WL11 and WL13), and it was clearly switched to programmed state after programming WL12. In addition, 3D FeNAND with a higher number of stacked cells was simulated using TCAD tool. The number of stacked cells was 32, 64, and 128 (fig. S12). The electrical characteristics of 3D FeNAND were characterized using the same program and block-erase operation method discussed above. All 3D FeNANDs were successfully programmed and block-erased using above voltage pulses, and the memory window was not significantly affected by the number of stacked cells, which confirmed that the 3D FeNAND could be operated with highly stacked structures. These results indicated that the suggested 3D FeNAND composed of FeTFTs with low power consumption and fast operation speed could replace 3D NAND flash memory.

Fig. 6 Device simulation of 3D FeNAND.

(A) Device structure of simulated 3D FeNAND. A single string containing 16 WLs, ground select line (GSL), and string select line (SSL) is simulated. The 30-nm-thick TiN, 24-nm-thick HfZrOx, and 10-nm-thick InZnOx are used as WL, ferroelectric gate insulator, and oxide semiconductor channel, respectively. SiO2 is used as oxide filler material. The thickness of SiO2 spacer between adjacent WLs is 30 nm. (B) Simulated polarization in HfZrOx layer after block-erase and program operations. First, all WLs are erased by block-erase operation. Then, WL11 and WL13 cells are programmed. Last, WL12 cell is programmed. Polarization in HfZrOx layer is clearly changed after block-erase and program operations. (C) Polarization change after block-erase and program operations. a.u., arbitrary units. (D) IBL-VWL curves in WL12 cell after block-erase and program operations.


We demonstrated a combination of ferroelectric HfZrOx and InZnOx oxide semiconductor channel as unique integration strategies to solve the key issues in ferroelectric memory transistors. The devices were fabricated using CMOS-compatible processes at low processing temperature (400°C) and showed fast operation speed (<10−6 s), low operation voltage (<5 V), and excellent endurance (>108 cycles), which were achieved by the synergistic effect of ferroelectric HfZrOx and InZnOx oxide semiconductor. We also investigated the potential of our ferroelectric memory as an alternative to conventional flash memory using an integrated FeNAND and a vertical FeTFT array. In FeNAND, the program disturbance was minimized by using the program-inhibit operation method. In program-inhibit operation, the polarization switching of ferroelectric layer was hindered by decreasing the difference in voltage between gate and channel. The states of memory cells in NAND strings were successfully confirmed by nondestructive read operation. The Ireadout for erased and programmed FeTFT memory cells exhibited distinguishable programmed and erased states. In addition, the string- and page-level NAND operations were demonstrated using the FeNAND array. Only the memory string that had all programmed cells showed the on state; when even one cell was erased, the string showed the off state. Vertical FeTFT array was fabricated by vertically stacking the TiN gate electrode and SiO2 insulating layer to investigate its feasibility for 3D FeNAND. We verified that the FeTFTs could be operated in the vertical structure, and operation mechanism was confirmed using the device simulation. Last, the possibility of ultrahigh-density 3D memory integration was confirmed by simulating program and block-erase operation in 3D FeNAND cells. These results suggest that ALD-based FeTFTs have the potential in future high-density 3D memory applications.



Hf[N(C2H5)CH3]4 [tetrakis(ethylmethylamido)hafnium (TEMAH)] and Zr[N(C2H5)CH3]4 [tetrakis(ethylmethylamido)zirconium (TEMAZ)] were purchased from UP Chemical, Korea. C10H28NSi2In4 [bis(trimethysilyl)amidodiethyl indium (INCA-1)] and Zn(C2H5)2 [diethylzinc (DEZ)] were purchased from iChems, Korea. Si wafers with 100-nm-thick thermally grown SiO2 were used as substrates.

Device fabrication

The devices were fabricated on the SiO2/Si substrate. The photolithography was done using a mask aligner (MA6, Suss MicroTec). An FeNAND array was fabricated by integrating FeTFTs. First, DC sputtering was used to deposit TiN on the SiO2/Si substrate as the gate electrode for FeTFT and as WLs for FeNAND. The TiN layer was patterned using a lift-off method. Then, 24-nm-thick HfZrOx film was deposited on the TiN/SiO2/Si by alternating ALD cycles of HfO2:ZrO2 at 280°C, using TEMAH, TEMAZ, and O3 as the Hf precursor, Zr precursor, and oxygen source, respectively. Electron beam evaporation was used to deposit Mo as source/drain electrodes for FeTFTs and as SL/BLs for FeNAND. The Mo layer was patterned using a lift-off method. A layer of 20-nm-thick InZnOx film was deposited at 150°C using INCA-1, DEZ, and O3 as an indium precursor, zinc precursor, and oxygen source, respectively. The InZnOx layer was patterned using a combination of lithography and wet etching. The channel length and width were 10 and 50 μm, respectively. Then, the devices were thermally annealed for 10 min at 400°C under N2 environment. Etching process was done to open the contacts for WLs. For the vertical FeTFT array, 100-nm-thick TiN and 50-nm-thick SiO2 layers were sequentially deposited using sputtering and plasma-enhanced chemical vapor deposition, respectively. TiN/SiO2/TiN/SiO2/TiN layers were etched by dry etch (NE-7800, ULVAC) using sulfur hexafluoride (SF6) plasma. The 24-nm-thick HfZrOx layer, 20-nm-thick InZnOx channel layer, and Mo source/drain electrodes were deposited using the same method described above.


All electrical properties were measured under ambient conditions and at room temperature. The electrical characteristics were obtained using a semiconductor parameter analyzer (4200A-SCS, Keithley Instruments). The ferroelectric characteristics were measured after applying 103 cycles of rectangular bipolar pulses (±7.2 V, 5 μs) for the wake-up of HfZrOx (fig. S1). The P-E curves were measured using a pulse measurement unit (4225-PMU, Keithley Instruments). PFM images were obtained using a scanning probe microscopy system (NX10, Park Systems). For PFM measurement, a cantilever that had a Pt-coated conductive tip was used to apply voltages to the sample, and the bottom electrode was grounded. An area of 2.5 μm by 2.5 μm (outer square regions) was poled by application of −6 V at a scan rate of 0.5 Hz; then, 1.5 μm by 1.5 μm (inner square regions) was scanned by application of 6 V at a scan rate of 0.5 Hz. After that, the reading process was performed over an area of 3 μm by 3 μm to verify the polarization states. The C-V curve was measured using an impedance analyzer (4194A, HP). Optical images of the devices were captured using an optical microscope (LV100ND, Nikon). The cross-sectional images of the devices were obtained using a high-resolution field-emission scanning electron microscope (JSM-7800F PRIME, JEOL). Simulations were conducted using Sentaurus TCAD (Synopsys Inc.) software.


Supplementary material for this article is available at

This is an open-access article distributed under the terms of the Creative Commons Attribution-NonCommercial license, which permits use, distribution, and reproduction in any medium, so long as the resultant use is not for commercial advantage and provided the original work is properly cited.


Acknowledgments: Funding: This work was supported by Samsung Research Funding and Incubation Center of Samsung Electronics under project no. SRFC-TA1903-05. The Sentaurus TCAD simulator was provided by the Electronic Design Automation (EDA) tool program of IC Design Education Center (IDEC) in Korea. Author contributions: J.-S.L. conceived and directed the research. J.-S.L., M.-K.K., and I.-J.K. designed and planned the experiment, analyzed the data, and wrote the manuscript. M.-K.K. and I.-J.K. performed the experiment and acquired the data. Competing interests: The authors declare that they have no competing interests. Data and materials availability: All data needed to evaluate the conclusions in the paper are present in the paper and/or the Supplementary Materials. Additional data related to this paper may be requested from the authors.
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