Science Advances

Supplementary Materials

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  • Fig. S1. Original data corresponding to Fig. 1B.
  • Fig. S2. Fabrication process of the CTFM array.
  • Fig. S3. Fabrication process of the pseudo-CMOS inverter array.
  • Fig. S4. TEM images of AuNP FG assembled using the LB method after the Box deposition using the PEALD process.
  • Fig. S5. TEM-EDS analysis of AuNPs embedded in an FG cell.
  • Fig. S6. Energy band diagrams of CTFM under three representative bias conditions.
  • Fig. S7. EFM images of the FG cell containing different amounts of charges at different locations according to the elapsed time after charge injection.
  • Fig. S8. PGM/ERS characteristics with operation voltages.
  • Fig. S9. PGM/ERS speed analysis of the CTFM array.
  • Fig. S10. Retention characteristics of a CTFM pixel for different memory states.
  • Fig. S11. Retention characteristics of the programmed state (30 V, 0.1 s) and the erased state (−40 V, 0.1 s).
  • Fig. S12. Changes in the transfer curves of a CTFM pixel after repetitive PGM and ERS cycles.
  • Fig. S13. Changes in transfer curves of a CTFM pixel (selected one) after programming or erasing peripheral ones.
  • Fig. S14. Stretching test of the CTFM pixels.
  • Fig. S15. Characteristic curves/simulation results of the pseudo-CMOS inverter and a transistor.
  • Fig. S16. PSpice simulation and experimental results of the pseudo-CMOS inverter.
  • Fig. S17. Effective gain and frequency response of the pseudo-CMOS inverter.
  • Fig. S18. Stretching test of the pseudo-CMOS inverter.
  • Fig. S19. Demonstration procedures and data storage scheme.
  • Fig. S20. Real-time monitoring of amplified ECG signals.
  • Table S1. Noise margins of the pseudo-CMOS inverter.

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